1. Field of the Invention
The present invention relates to communication networks. In particular, the present invention relates to improving synchronization of elements within an asynchronous serial data network.
2. Background of the Invention
In data communications there are two distinct formats for data transfer:
serial and parallel. In serial data transfer, data is transferred one symbol at a time over a single communications channel or link, for example a wire, optical fiber, or wireless connection. In parallel data transfer, multiple symbols are transferred simultaneously over a corresponding multiple of channels. Data is typically represented in binary format and a symbol may encode 1 or more binary data bits such as a one (1) or zero (0).
One advantage of serial communication over parallel communication is that a serial interface requires fewer physical resources to implement, such as transmit and receive circuitry, printed circuit board area, integrated circuit pins, connectors and cables. In short, a serial interface is advantageous for implementing low-cost, compact and portable systems. For instance, some battery management systems include large numbers of serially connected lithium-ion battery cells. In these systems, hundreds of cells of 3-4 volts (V) may be connected in series to battery packs as high as 800V or more. These battery management systems are use in several applications, such as hybrid electric automobiles, buses, golf-carts, fork-lifts, power-boats, etc.
A universal asynchronous receiver and transmitter (UART) is one example of a device that implements a serial interface. The UART is ubiquitous in modern computing and communications and has a long history in the art. A standard implementation of a UART is found in RS-232 transceivers. The RS-232 specification dates back to the 1960s, when it was first released by the Electronic Industries Association (EIA). The specification has evolved over time, incorporating higher data rates and closing compatibility gaps. The current version of the RS-232 specification is ETA/TIA-232-F, dated October 1997. The protocol benefited from the availability of integrated circuits (IC) that include complexity to handle these communications at reasonable cost.
A UART comprises two serial channels, one for transmitting data and one for receiving data, operating in full-duplex. In the UART protocol data is transmitted in frames, one bit per symbol, where the data is represented in binary format using non-return to zero (NRZ) encoding. A typical UART frame includes a start bit, 8 data bits, and a stop bit. Other variants are possible (additional stop bits, fewer data bits, parity bits for rudimentary error detection, etc.). RS-232 bus drivers invert as well as level shift, so a logic 1 is a negative voltage on the bus, and a logic 0 is a positive voltage.
A UART is ordinarily constructed using clocked or synchronous logic. The term “asynchronous” arises because a clock signal is not transmitted as part of the interface protocol. In fact, the clocks of the transmitting and receiving UARTs may have differing phase and frequency. Therefore, when two UARTs communicate, both transmitter and receiver must agree on the symbol rate, also called the baud rate, in advance. The receiving UART recognizes the limits of a data frame by observing the start and stop bits, and determines the best data sampling point for each bit based on the predetermined baud rate.
UART receivers commonly synchronize themselves to data frames using an oversampling clock. For instance, a UART may use a sample clock that is 16 times the baud rate. A new frame is recognized by a falling edge at the beginning of a start bit. The UART resets a counter on this falling edge, and expects the middle of the start bit to occur after 8 clock cycles, and the mid point of each subsequent bit to appear every 16 clock cycles thereafter. The bits are sampled at each mid point. Another method involves sampling each bit not simply once at the mid point (cycle 8 out of 16) but also on the cycle before and after the mid point (cycles 7, 8 and 9 out of 16). A vote-of-three is applied to the samples, thereby avoiding a data error caused by noise corrupting any one sample.
The frequency stability of the transmitter and receiver clocks is a concern when attempting to transfer data correctly. If the receiving and transmitting UART clock frequencies are too far apart, data errors may occur. The timing of the data frame is based on the transmitting UART's clock. The receiving UART synchronizes to the frame based on detection of the start bit. As the remaining bits in the frame are sampled, any frequency mismatch between transmitter and receiver accumulates so that the sampling point of the bit deviates from the actual mid point. A data error is caused when this deviation exceeds the boundaries of the valid data window for the bit and the bit is sampled too early or too late. This can be compounded by the fact that the valid data window is reduced by finite (and typically slow) transmission rise and fall times such as those caused by a long, capacitive RS-232 bus, making it more important to sample close to the mid point where the level has settled. Clock frequency tolerances are generally described in terms of percentages. For instance, a frequency mismatch between transmitter and receiver in a normal scenario should not exceed approximately 3-4%; the exact tolerance dependent on the oversampling frequency and size of the valid data window for a bit. Exceeding this mismatch leads to a cumulative drift of the data sampling point after the initial synchronization with the start bit, and can result in sampling errors, such as sampling during the undefined region of the bit transition or even sampling the wrong bit.
Crystal oscillators have been used to match transmit and receive clocks, however, these are too expensive for cost-sensitive applications and can consume too much power for low-power applications. RC oscillators are an alternative commonly found in embedded circuits but they are sensitive to process, voltage, and temperature variations, i.e. the frequency changes as the conditions change. Compensating for these effects requires design of larger and higher current circuitry and time consuming device trimming, all of which is undesirable. For instance, in the battery management system described above, the volatile nature of lithium-ion battery cells requires careful monitoring of the voltage and temperature of the cells. Particularly during charge and discharge, monitoring and controlling avoids over-voltage (over-charge), under-voltage (over-discharge) and over and under temperature conditions. Special battery management integrated circuits (ICs) are developed to handle this job. These data acquisition devices contain inputs to monitor the cell voltage and temperature and circuitry to convert these quantities from analog to digital form. Because the voltage of each cell and temperature of each cell (or a small group of cells) must be monitored individually, it is impractical to build one device to monitor the hundreds of cells. The device would be too large (have too many pins) and the high voltages in the system prohibit constructing this device with commonly available silicon technologies. In addition, the physical dimensions of a battery pack are such that if all cells had to be wired back to a single device it would require long wires congested wiring.
UARTs may be designed to operate at a variety of baud rates. It is desirable to maintain the same number of samples per bit for each different baud rate in order to simplify the logic design and also provide a scaling of the immunity to sampled noise proportional to the baud rate. This is typically accomplished by providing a system clock to the UART with a frequency greater than the highest baud rate and using an integer divider to generate the desired sampling clock frequency. Table 1 illustrates this method for different baud rates assuming an 8.192 MHz system clock is used to generate a 16 times over-sampling clock. For a baud rate of 9600 bits per second, the ideal sampling clock would be 9600×16=153.6 kHz. However, using the integer divider the closest frequency that can be generated is 154.566 kHz. This represents an error of 0.629%, which is acceptable for reliable data transmission.
TABLE 1SampleCenteringBAUD[1:0]Baud RateNSample ClockClock errorerror0 0 9600 bps53154.566 KHz0.629% −5.93%0 119200 bps27303.407 kHz−1.235% 11.88%1 038400 bps13630.154 kHz2.56%−23.8%1 176800 bps71170.285 kHz 4.76%−47.5%
Further examination of Table 1 shows that the sampling clock error increases as the baud rate increases. Although the error for 38400 bps (2.56%) is marginally acceptable, the error for 76800 bps is clearly unacceptable and will result in data sampling errors. Further this error does not account for additional drift of the system clock due to temperature variations, etc. Nor does it account for any error of the clock in the transmitter.
One method that may be used to mitigate the effects of clock mismatch in asynchronous serial communications involves alternative signaling schemes, such as continuous bi-frequency encoding rather than NRZ encoding. Unlike NRZ encoding, continuous bi-frequency encoding provides a signal transition at the start of every bit. A zero and one data bit are distinguished by the absence or presence of a second transition midway through the bit time. For example, a zero is characterized by a single transition at the start of the bit time and no additional transitions for the remainder of the bit time. In contrast, a one is characterized by a first transition at the start of the bit time and a second transition midway through the bit time.
Continuous bi-frequency encoding is tolerant of greater clock frequency mismatch because the receiving device can synchronize to the start of each bit rather than only the start bit. In fact, the start and stop bits in the traditional UART protocol are no longer necessary. Because each bit is synchronized, the error does not accumulate as each subsequent bit is received and clock frequency mismatches greater than 20% can be tolerated when using 16 times oversampling. However, although the tolerance is improved, further improvement is still desirable.
Asynchronous serial interfaces are commonly used to connect nodes in various network topologies such as a ring network. A ring network is a network topology in which the nodes are connected in a closed loop. Each node is connected to exactly two other nodes such that starting at any particular node, traversing a path through all other nodes will lead back to the starting node. Each node is a connection point that represents a system or device, and the devices in the ring communicate with each other through the connections between the nodes. Intermediate nodes are able to pass data between their adjacent nodes such that non-adjacent nodes can communicate with one another around the ring. The communication circuits in different nodes of the network do not normally share a common clock, i.e. they are unsynchronized.
Therefore, there is a need for an improved system and method for serial communication between devices to overcome the problems of unsynchronized clocks, and which can be applied in a communications network of various topologies such as a ring network.